Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

作者: Manoj Kumar , Subhasis Haldar , Mridula Gupta , R S Gupta

DOI: 10.1088/0268-1242/31/10/105013

关键词:

摘要: The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs). physics of material engineered (GME)-SB-GAA MOSFETs LC still unexplored. An explicit model GME-SB-GAA-MOSFETs with incorporation (N it) developed. To accurately minimum channel density has been taken into account. renders how +/− affects device subthreshold performance. One-dimensional (1D) Poisson's and 2D Laplace equations have solved two different regions (fresh damaged) metal work-functions. LCs are considered at drain side low work-function as N it more vulnerable towards drain. For reduction mobility degradation, lightly doped considered. proposed also includes effect height lowering metal–semiconductor interface. developed results verified using numerical simulation data obtained by ATLAS-3D simulator excellent agreement observed between analytical results.

参考文章(36)
William McMahon, Yoann Mamy-Randriamihaja, Balaji Vaidyanathan, Tanya Nigam, Ninad Pimparkar, From Atoms to Circuits: Theoretical and Empirical Modeling of Hot Carrier Degradation Hot Carrier Degradation in Semiconductor Devices. pp. 3- 27 ,(2015) , 10.1007/978-3-319-08994-2_1
Yogesh Pratap, Subhasis Haldar, Radhey Shyam Gupta, Mridula Gupta, Localized Charge-Dependent Threshold Voltage Analysis of Gate-Material-Engineered Junctionless Nanowire Transistor IEEE Transactions on Electron Devices. ,vol. 62, pp. 2598- 2605 ,(2015) , 10.1109/TED.2015.2441777
Markus Jech, Yannick Wimmer, Florian Rudolf, Hubert Enichlmair, Jong-Mun Park, Hajdin Ceric, Tibor Grasser, Prateek Sharma, Stanislav Tyaginov, The role of cold carriers and the multiple-carrier process of Si–H bond dissociation for hot-carrier degradation in n- and p-channel LDMOS devices Solid-state Electronics. ,vol. 115, pp. 185- 191 ,(2016) , 10.1016/J.SSE.2015.08.014
N. Arora, MOSFET Models for VLSI Circuit Simulation Microelectronics Journal. ,vol. 26, ,(1993) , 10.1016/0026-2692(95)90019-5
Michele De Marchi, Davide Sacchetto, Jian Zhang, Stefano Frache, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli, Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity IEEE Transactions on Nanotechnology. ,vol. 13, pp. 1029- 1038 ,(2014) , 10.1109/TNANO.2014.2363386
Chandrima Mondal, Abhijit Biswas, 2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design IEEE Transactions on Electron Devices. ,vol. 60, pp. 2525- 2531 ,(2013) , 10.1109/TED.2013.2270085