Source and Drain Junction Engineering for Enhanced Non-Volatile Memory Performance

摘要: There is strong demand to maintain the trend of increasing bit density and reducing cost in Flash memory technology. To this end, aggressive scaling device dimension multi-level cell (MLC) or multi-bit (MBC) have been proposed NAND NOR architectures. However, especially memory, expected rise near future, because process will increase more rapidly than shrink rate. One solution avoid such challenges use three dimensionally stacked array structures, based on polycrystalline silicon (poly-Si). The utilization poly-Si channel not only increases pass disturbs but also reduces worst case string current. Indeed, for every doubling density, current halves. Since these devices source/drain (S/D) regions are formed (i.e., a junction-free structure), (all cells with high threshold voltage (VT)) quickly tend toward unreadably low values as (Walker, 2009). Therefore, it worthwhile note that impact S/D structures becomes important. Moreover, Fowler-Nordheim (FN) tunneling programming still very slow certain applications require high-speed operation. In length has threatened continued approaching its end point. For uniform hot electron injection (CHEI) programming, robust margin punch-through pre-requisite transistors. CHEI aggravates immunity against by drain level trigger CHEI. It clear window guarantee both speed from disturbance narrowed scales down. efficiency compromising vertical lateral fields parasitic resistance at junctions impose constraint size reduction. Consequently, lower effective program due an extremely scaled results small VT thereafter retards speed. Herein engineering enhanced performance two novel demonstrated: (i) dopant-segregated Schottky-barrier (DSSB), (ii) junctionless MOSFET. First, we utilized metallic silicide charge trapping cells. They boosted even bias aid abrupt band bending edge metal silicided junctions. Second,