Yield-preferred via insertion based on novel geotopological technology

作者: Fangyi Luo , Yongbo Jia , Wayne Wei-Ming Dai

DOI: 10.1145/1118299.1118469

关键词:

摘要: Yield-preferred via insertion is an effective method to reduce the yield loss caused by failures. The existing methods apply redundant-cut vias in metal layers are not efficient nor adequate. In this paper, we present and yield-preferred based on a novel geotopological layout platform, GEOTOP. Our chooses most yield-favored candidate insert it into without causing any design rule violations. Experiments with real industry designs show that our can achieve very high rate of increasing die size within acceptable running time.

参考文章(11)
Andrew B. Kahng, Y. C. Pati, Subwavelength lithography and its potential impact on design and EDA Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99. pp. 799- 804 ,(1999) , 10.1145/309847.310072
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong, Redundant-via enhanced maze routing for yield improvement asia and south pacific design automation conference. ,vol. 2, pp. 1148- 1151 ,(2005) , 10.1145/1120725.1120927
R.M. Warner, Applying a composite model to the IC yield problem IEEE Journal of Solid-State Circuits. ,vol. 9, pp. 86- 95 ,(1974) , 10.1109/JSSC.1974.1050474
Jong-Yeol Lee, In-Cheol Park, Timed compiled-code functional simulation of embedded software for performance analysis of SOC design IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 22, pp. 1- 14 ,(2003) , 10.1109/TCAD.2002.805721
Wayne Wei-Ming Dai, Man-Fai Yu, Joel Darnauer, Interchangeable pin routing with application to package layout international conference on computer aided design. pp. 668- 673 ,(1996) , 10.5555/244522.244954
Shuo Zhang, W. Dai, TEG: a new post-layout optimization method IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 22, pp. 446- 456 ,(2003) , 10.1109/TCAD.2003.809652
W.W.-M. Dai, D. Staepelaere, J. Jue, T. Dayan, Cost-driven layout for thin-film MCMs ieee multi chip module conference. pp. 174- 178 ,(1993) , 10.1109/MCMC.1993.302131
K.Y.Y. Doong, R.C.J. Wang, S.C. Lin, L.J. Hung, C.C. Chiu, D. Su, K. Wu, K.L. Young, Y.K. Peng, Stress-induced voiding and its geometry dependency characterization international reliability physics symposium. pp. 156- 160 ,(2003) , 10.1109/RELPHY.2003.1197737
T.C. Huang, C.H. Yao, W.K. Wan, C.C. Hsia, M.S. Liang, Numerical modeling and characterization of the stress migration behaviour upon various 90 nanometer Cu/Low k interconnects international interconnect technology conference. pp. 207- 209 ,(2003) , 10.1109/IITC.2003.1219755