IC layout adjustment method and tool for improving dielectric reliability at interconnects
作者： Andrew B. Kahng , Tuck Boon Chan
DOI:
关键词:
摘要: Method for adjusting a layout used in making an integrated circuit includes one or more interconnects the that are susceptible to dielectric breakdown selected. One selected adjusted increase via wire spacing with respect at least and of interconnects. Preferably, selecting analyzes signal patterns interconnects, estimates stress ratio based on state probability routed nets layout. An annotated is provided describes distances by which segment edges be shifted. Adjustments can include thinning shifting segments, rotation vias.
lens.org 参考文章(29)
Kyoko Izuha, Satoshi Tanaka, Semiconductor device pattern verification method, semiconductor device pattern verification program, and semiconductor device manufacturing method ,(2009)
Satyanarayana V. Nitta, Sebastian U. Engelmann, Eric A. Joseph, Benjamin Fletcher, Cyril Cabral, Interconnect structure for improved time dependent dielectric breakdown ,(2010)
Paul Brown, Off-width pitch for improved circuit card routing ,(2005)
James W. Adkisson, Benjamin T. Voegeli, Steven H. Voldman, Natalie B. Feilchenfeld, Jeffrey P. Gambino, Howard S. Landis, Michael J. Zierak, Modifying layout of IC based on function of interconnect and related circuit and design structure ,(2008)
Jason Hibbeler, Anthony Stamper, John Cohn, Jed Rankin, Circuit layout methodology ,(2007)
Thaddeus John Gabara, Tarek Chaker Jomaa, Variable rotational assignment of interconnect levels in integrated circuit fabrication ,(2003)
Olivier Pribetich, Olivier Omedes, Roland Ruehl, Ya-Chieh Lai, Frank E. Gennari, Wilbur Luo, System and method for automated real-time design checking ,(2011)
Kensuke Kageyama, Electro-mechanical transducer, an electro-mechanical converter, and manufacturing methods of the same ,(2009)
Dennis J. Ciplickas, David M. Stashower, Kimon Michaels, Joseph C. Davis, Larg H. Weiland, Brian E. Stine, Christopher Hess, John Kibarian, Sherry F. Lee, Purnendu K. Mozumder, System and method for product yield prediction ,(2000)
Tuck-Boon Chan, Andrew B. Kahng, Post-routing back-end-of-line layout optimization for improved time-dependent dielectric breakdown reliability Design for Manufacturability through Design-Process Integration VII. ,vol. 8684, ,(2013) , 10.1117/12.2011645