High throughput hardware architecture for (1440,1344) low-density parity-check code utilizing quasi-cyclic structure
作者： Hiroyuki Yamagishi , Makoto Noda
DOI: 10.1109/TURBOCODING.2008.4658676
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摘要: High throughput architecture of an encoder and a decoder for quasi-cyclic low-density parity-check (LDPC) code is proposed. A new systematic encoding method carried out by polynomial manipulation. The proposed architecture, where the check-node process split into two processes so that memory access becomes column-wise, enables overlapped message-passing any matrix. hardware utilizing structure does not require complex multiplexers. Hardware employing (1440,1344) LDPC designed high millimeter wave application evaluated using 65 nm CMOS technology. gate count 3 Gbps 6 2.5 k 3.1 k, respectively, 8 iterations 304 409 respectively. bit-error rate 10-6 obtained at Eb/N0 5.9 dB, estimated power consumption 58 mW 86 Gbps.
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