Low-power digital design

作者: M. Horowitz , T. Indermaur , R. Gonzalez

DOI: 10.1109/LPE.1994.573184

关键词:

摘要: … in low-power devices and design techniques. While many papers have been published describing power-saving techniques for use in digital … trade-offs in low-power design. The next …

参考文章(10)
N.K. Yeung, Y.-H. Sutu, T.Y.-F. Su, E.T. Pak, C.-C. Chao, S. Akki, D.D. Yau, R. Lodenquai, The design of a 55SPECint92 RISC processor under 2W international solid-state circuits conference. pp. 206- 207 ,(1994) , 10.1109/ISSCC.1994.344668
A. Chandrakasan, A. Burstein, R.W. Brodersen, A low power chipset for portable multimedia applications international solid-state circuits conference. pp. 82- 83 ,(1994) , 10.1109/ISSCC.1994.344718
E.K. Tsern, A.C. Hung, T.H.Y. Meng, Video compression for portable communication using pyramid vector quantization of subband coefficients ieee workshop on vlsi signal processing. pp. 444- 452 ,(1993) , 10.1109/VLSISP.1993.404461
Saed G. Younis, Thomas F. Knight, Practical implementation of charge recovering asymptotically zero power CMOS Proceedings of the 1993 symposium on Research on integrated systems. pp. 234- 250 ,(1993)
Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen, Low-Power CMOS Digital Design IEICE Transactions on Electronics. pp. 371- 382 ,(1992)
J.G. Koller, W.C. Athas, Adiabatic Switching, Low Energy Computing, And The Physics Of Storing And Erasing Information Workshop on Physics and Computation. pp. 267- 270 ,(1992) , 10.1109/PHYCMP.1992.615554
R.H. Dennard, F.H. Gaensslen, Hwa-Nien Yu, V.L. Rideout, E. Bassous, A.R. LeBlanc, Design of ion-implanted MOSFET's with very small physical dimensions IEEE Journal of Solid-State Circuits. ,vol. 9, pp. 256- 268 ,(1974) , 10.1109/JSSC.1974.1050511
D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi, Open/folded bit-line arrangement for ultra-high-density DRAM's IEEE Journal of Solid-state Circuits. ,vol. 29, pp. 539- 542 ,(1994) , 10.1109/4.280706
B.P. Brandt, B.A. Wooley, A low-power, area-efficient digital filter for decimation and interpolation IEEE Journal of Solid-state Circuits. ,vol. 29, pp. 679- 687 ,(1994) , 10.1109/4.293113
T. Indermaur, M. Horowitz, Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design Proceedings of 1994 IEEE Symposium on Low Power Electronics. pp. 102- 103 ,(1994) , 10.1109/LPE.1994.573221