Method of preparing an integrated circuit die for imaging
作者： Lev Klibanov , Sherri Lynn Griffin
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摘要: Integrated circuit dies are prepared for imaging by completely etching away all metal from the lines without removing barrier layers that underlie lines. The vias may also be removed, especially if they formed same as lines, in copper damascene circuits. This provides high contrast images permits layout extraction software to readily distinguish between and vias.
google.de 参考文章(13)
George Chamberlain, Larry Lam, Computer-assisted design analysis method for extracting device and interconnect information ,(1997)
Michael A. Dukes, Determination of functionality for integrated circuit modules ,(1998)
Kenneth K. Yu, C. Neil Berglund, Automated system for extracting design and layout information from an integrated circuit ,(1990)
Thomas Kapler, Stephen Begg, Jason Abt, Computer aided method of circuit extraction ,(2001)
Su-Ping Teong, Etch stop for copper damascene process ,(2002)
Carmencita I. Robbins, Joseph J. Dlugokecki, Gerardo Bagalawig Nazareno, Steven David Swendrowski, Method for deconstructing an integrated circuit package using lapping ,(2002)
Vyacheslav L. Zavadsky, Stephen Begg, Jason Abt, Edward Keyes, Val Gont, Method of Design Analysis of Existing Integrated Circuits ,(2008)
Lap-Wai Chow, William M. Clark, James P. Baukas, Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations ,(2002)
George Chamberlain, Ghassam Naim, Alexei Ioudovski, John Scott Thomas, Method to extract circuit information ,(1997)
Julia Elvidge, Terry Ludlow, David Skoll, Pierrette Breton, Bryan Socransky, Ray Haythornthwaite, Louise Weaver, Dick James, Michael Phaneuf, Automatic focused ion beam imaging system and method ,(1999)