The design of an area efficient segmented DAC

摘要: DAC architectures reported in the literature use segmentation schemes involving more thermometer and less binary bits, order to guarantee a better dynamic static performance. In this paper, novel technique is proposed minimize glitch section of segmented current steering through custom design latches. This enables bits than what literature. Using technique, 12 bit 400MSPS with 8 4 designed using AMI 350 nm n-well CMOS process. A MSB also conventional approach. The performance above two DACs are obtained ELDO SPICE simulations. From these, it found that INL, DNL SFDR at 1 MHz for 0.7 LSB, 0.65 LSB 79 dB whereas those architecture 0.63 0.04 87 respectively. With only marginal degradation performance, results lower silicon area routing complexity. reduction digital decoder no. latches required higher update rate DAC. estimated about 30% times scheme.