Optimum Segmentation for High Speed Current Steering Digital-to-Analog Converters
作者： J.A. Hegt , A.H.M. van Roermund , P.C.W. van Beek
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摘要: When designing a Current Steering Digital to Analog Converter, major architectural parameter is the number of bits in partitioning between thermometer and binary segments. This called segmentation. The DAC designer has choose optimum amount segmentation taking into account physical problems associated with steering DACs low have advantage that they are simple. They only need few current sources switches. A disadvantage possible larger DNL compared converters Converters lower DNL, but output conductance, capacitance synchronization increase also area power needed increases.
narcis.nl参考文章(10)
Paul G. Jespers, G. Lancaster, E.W. Williams, Integrated converters : D to A and D architectures, analysis and simulation Oxford University Press. ,(2001)
Behzad Razavi, Principles of Data Conversion System Design ,(1994)
K. Doris, D. Leenaerts, A. v. Roermund, High-speed Digital to Analog Converter issues with applications to Sigma Delta Modulators Analog circuit design : structured mixed-mode design, multi-bit sigma-delta converters, short range RF circuits. pp. 205- 233 ,(2002) , 10.1007/0-306-47951-6_10
Behzad Razavi, Design of Analog CMOS Integrated Circuits ,(1999)
Rudy J. van der Plassche, Integrated Analog-To-Digital and Digital-To-Analog Converters ,(1994)
J Jacob Wikner, Studies on CMOS Digital-to-Analog Converters Linköping University Electronic Press. ,(2000)
K. Doris, A. van Roermund, D. Leenaerts, Mismatch-based timing errors in current steering DACs international symposium on circuits and systems. ,vol. 1, pp. 977- 980 ,(2003) , 10.1109/ISCAS.2003.1205729
Chi-Hung Lin, K. Bult, A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/ IEEE Journal of Solid-state Circuits. ,vol. 33, pp. 1948- 1958 ,(1998) , 10.1109/4.735535
M.A.F. Borremans, M.S.J. Steyaert, W. Sansen, A. van den Bosch, A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter IEEE Journal of Solid-state Circuits. ,vol. 36, pp. 315- 324 ,(2001) , 10.1109/4.910469
J.J. Wikner, Nianxiong Tan, Modeling of CMOS digital-to-analog converters for telecommunication IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing. ,vol. 46, pp. 489- 499 ,(1999) , 10.1109/82.769797