Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding

摘要: This paper presents efficient VLSI architectures of the shape-adaptive discrete cosine transform (SA-DCT) and its inverse (SA-IDCT) for MPEG-4. Two challenges encountered during exploitation more SA-DCT SA-IDCT are addressed. One challenge is to handle architectural irregularity due nature. The other one provide acceptable throughput using minimal hardware. In algorithm-level optimization, this work exploits numerical properties found in matrices various lengths, derives a fine-grained zero-skipping scheme IDCT which can perform 22.6% than common vector-based coarse-grained does. architecture-level design, 1-D variable-length DCT/IDCT designed on basis proposed. An auto-aligned transpose memory that aligns data different lengths also incorporated. addition, zero-index table included support SA-IDCT. synthesized designs implemented UMC 0.18-mum technology. architecture has 26 635 gates, average cycle-throughput 0.66 pixels/cycle, comparable proposed architectures. On hand, 29 960 6.42 pixels/cycle. While decoding CIF@30FPS, clocked at 0.7 MHz, power consumption 0.14 mW. Both an order better those existing