作者: So Young Kang , Seung Tak Ryu , Chul Soon Park
DOI: 10.1109/CSICS.2010.5619663
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摘要: A dB-linear programmable gain amplifier (PGA)utilizing weighted input transistors, is implemented in a 0.18 μm CMOS process. The weighed transistor units with constant current-density enable insensitive gain-steps while maintaining the load impedance condition. range can cover from -18 dB to +30 6 steps, and error less than 1 dB. 3 bandwidth (BW) 60 MHz P1dB -36 dBm at maximum gain. chip area as small 0.12 mm2 total power consumption only 2.5 mW under 1.8 V supply.