Integrated circuit and method for fabricating the same

作者: Mou-Shiung Lin , Jin-Yuan Lee

DOI:

关键词:

摘要: A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having thickness of between 5 μm and 27 over semiconductor substrate, passivation layer on the trace, wherein silicon nitride oxide nitride, or oxynitride oxynitride.

参考文章(101)
Vance Dolvan Archer, Philip William Seitzer, Taeho Kook, Sailesh M. Merchant, Thomas B. Gans, Joze E. Antol, Rafe Carl Mengel, Daniel Patrick Chesire, Reinforced bond pad for a semiconductor device ,(2004)
Patricia Ellen Marmillion, John Edward Cronin, Wayne John Howell, Dennis Arthur Schmidt, Anthony Palagonia, Howard Leo Kalter, Bernadette Ann Pierson, Methods for precise definition of integrated circuit chip edges ,(1997)
T.J. Maloney, W. Kan, Stacked PMOS clamps for high voltage power supply protection electrical overstress electrostatic discharge symposium. pp. 70- 77 ,(1999) , 10.1109/EOSESD.1999.818992
Ching-San Lin, Hsien-Tsung Liu, Chien-Kang Chou, Method of metal sputtering for integrated circuit metal routing ,(2006)
Edward R. Prack, Lei L. Mercado, James Jen-Ho Wang, Young Sir Chung, Vijay Sarihan, Semiconductor power device and method of formation ,(2001)
Hsin-Jung Lo, Chiu-Ming Chou, Mou-Shiung Lin, Chien-Kang Chou, Chip structure and method for fabricating the same ,(2008)
James H. Kleffner, George F. Carney, Addi Burjorji Mistry, Vijay Sarihan, Method and apparatus for stress relief in solder bump formation on a semiconductor device ,(1998)