作者: Eric Paton , Jonathan G. Kluth , Peter G. Borden
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摘要: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the process. In one embodiment, a test structure including or more regions is formed production (e.g. simultaneously with transistors) and dimension(s) are measured, used estimate other wafer, e.g. transistors. Doped structures can located at regularly spaced intervals relative another, alternatively varying spacings between adjacent regions. Alternatively addition, multiple single regular spatial each structure, while different have intervals.