Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis
作者： Sisir Kumar Jena , Santosh Biswas , Jatindra Kumar Deka
DOI: 10.1109/VDAT50263.2020.9190571
关键词:
摘要: A gigantic amount of test pattern covering all faults is required to attain a high quality in modern VLSI testing. With this, the Test Data Volume (TDV) rises, which leads an increase Application Time (TAT) as well power requirement. This paper proposes Fault-based Approximate Testing (FAT) technique that generates patterns only for distinguished faults. The basic idea identifying set (tolerable faults) can be ignored and left untested. remaining (intolerable are tested by generating those We examine impact overlooking some injecting stuck-at appropriate place netlist. Deviation output analyzed respect application-specific error threshold. experimental result shows irrespective erroneous produced, these circuits used kinds error-tolerant applications like image/video processing, speech digital communications. Along with above benefit number fault-sites reduces 40–50%, reduction patterns.
sci-hub.st 参考文章(12)
Zhigang Jiang, S.K. Gupta, An ATPG for threshold testing: obtaining acceptable yield in future processes international test conference. pp. 824- 833 ,(2002) , 10.1109/TEST.2002.1041836
M.A. Breuer, Intelligible test techniques to support error-tolerance asian test symposium. pp. 386- 393 ,(2004) , 10.1109/ATS.2004.51
M.C. Hansen, H. Yalcin, J.P. Hayes, Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering IEEE Design & Test of Computers. ,vol. 16, pp. 72- 80 ,(1999) , 10.1109/54.785838
Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue, A Practical Approach to Threshold Test Generation for Error Tolerant Circuits asian test symposium. pp. 171- 176 ,(2009) , 10.1109/ATS.2009.19
Jeremy Schlachter, Vincent Camus, Krishna V. Palem, Christian Enz, Design and Applications of Approximate Circuits by Gate-Level Pruning IEEE Transactions on Very Large Scale Integration Systems. ,vol. 25, pp. 1694- 1702 ,(2017) , 10.1109/TVLSI.2017.2657799
Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio, Towards approximation during test of Integrated Circuits design and diagnostics of electronic circuits and systems. pp. 28- 33 ,(2017) , 10.1109/DDECS.2017.7934574
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio, Testing approximate digital circuits: Challenges and opportunities 2018 IEEE 19th Latin-American Test Symposium (LATS). pp. 1- 6 ,(2018) , 10.1109/LATW.2018.8349681
Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu, Test and Reliability in Approximate Computing Journal of Electronic Testing. ,vol. 34, pp. 375- 387 ,(2018) , 10.1007/S10836-018-5734-9
Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio, On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits design and diagnostics of electronic circuits and systems. pp. 85- 90 ,(2018) , 10.1109/DDECS.2018.00022
Arnaud Virazel, Alberto Bosio, Patrick Girard, Imran Wali, Mario Barbareschi, Marcello Traiola, Can we Approximate the Test of Integrated Circuits WAPCO: Workshop On Approximate Computing. ,(2017)