Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections

摘要: Application of the chemical mechanical polishing silicon dioxide used as interlevel dielectric in manufacture VLSI chips has led to development a relatively simple process for fabrication device wiring on such chips. The is remove from tops interconnect studs and produce planarized surface ready next level wiring. characteristics this were studied both blanket films oxide wafers with topography. Empirical relationships found, results applied manufacture, resulting simplification while increasing chip reliability yield.