Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology

摘要: A new method of forming selective salicide is described, whereby low resistance formed on exposed MOSFET CMOS, narrow polysilicon gates and lightly doped source/drains (LLD) without affecting device electrical performance. This invention describes a process titanium CMOS devices using ion implantation for effective mixing between two-step deposition process. First, thin layer deposited gate source/drain regions. Second, energy Si+ performed with peak dose targeted to be just below the Ti/Si interface. Third, an initial rapid thermal anneal (RTA) followed by etch remove unwanted, excess titanium. The final step another fully convert silicide from C49 crystal structure preferred C54 structure, resistivity. Hence, resistivity self-aligned polygates