Mechanisms for forming copper pillar bumps using patterned anodes
作者： Ming-Da Cheng , Chih-Wei Lin , Chung-Shi Liu , Wen-Hsiung Lu
DOI:
关键词:
摘要: The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die across the wafer. In addition, above allow forming bumps with different heights to be integrated elements on a substrate heights. Bumps expand application copper post enable further chip integration.
google.co.in参考文章(144)
Reijiro Shoji, Kazuto Saitoh, Bump structure, bump forming method and package connecting body ,(1996)
Chien Ling Hwang, Chung-Shi Liu, Yi-Wen Wu, Pillar bump with barrier layer ,(2010)
Paul A. Lauro, Da-Yuan Shih, Minhua Lu, Sung K. Kang, Electromigration-resistant under-bump metallization of nickel-iron alloys for sn-rich solder bumps of pb-free flip-chip applications ,(2009)
Peter Salmon, Electro-optic interconnection apparatus and method ,(2006)
Mou-Shiung Lin, Reliable metal bumps on top of I/O pads with test probe marks ,(2001)
Steve Xin Liang, Thermal mechanical flip chip die bonding ,(2008)
Kang-Wook Lee, Sung-min Sim, Se-young Jeong, Soon-bum Kim, Young-hee Song, Ung-Kwang Kim, Method for manufacturing wafer level chip stack package ,(2005)
Chen-Shien Chen, Kuo-Ching Hsu, Backside Connection to TSVs Having Redistribution Lines ,(2008)
Kate E. Fey, Lee J. Mandell, Charles L. Byers, Space-saving packaging of electronic circuits ,(2003)
Pei-Haw Tsao, Han-Ping Pu, Kuo-Chin Chang, Enhanced copper posts for wafer level chip scale packaging ,(2010)