Circuit simulation method

作者: Kenta Yamada

DOI:

关键词:

摘要: A exemplary aspect of the present invention is a simulation method for semiconductor circuit that includes: resistor; plurality contacts arranged at regular intervals in longitudinal direction and width resistor on terminal region wiring line formed contacts, including: defining ratio parasitic-resistance by between two neighboring to resistance one as constant k; modeling net using k, including contacts.

参考文章(12)
Morihisa Hirata, Tetsuya Katou, Tomohiro Kitayama, Susumu Kobayashi, Mototsugu Okushima, ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device ,(2007)
R.C.Y. Fang, K.-Y. Su, J.J. Hsu, A two-dimensional analysis of sheet and contact resistance effects in basic cells of gate-array circuits IEEE Journal of Solid-state Circuits. ,vol. 20, pp. 481- 488 ,(1985) , 10.1109/JSSC.1985.1052333
S.J. Proctor, L.W. Linholm, J.A. Mazer, Direct measurements of interfacial contact resistance, end contact resistance, and interfacial contact layer uniformity IEEE Transactions on Electron Devices. ,vol. 30, pp. 1535- 1542 ,(1983) , 10.1109/T-ED.1983.21334
A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, K. DeMeyer, K. DeMeyer, Analysis of the parasitic S/D resistance in multiple-gate FETs IEEE Transactions on Electron Devices. ,vol. 52, pp. 1132- 1140 ,(2005) , 10.1109/TED.2005.848098
P. Larsson, Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance IEEE Journal of Solid-state Circuits. ,vol. 32, pp. 574- 576 ,(1997) , 10.1109/4.563679
Kunio Ono, 邦夫 小野, Design verification device ,(2007)