Strain and lattice engineering for Ge FET devices

摘要: One of the main challenges to creating a GeOI-based FET is simply create high-quality single-crystal layer for channel material. Due low cost and wide availability Si substrates, most popular approach Ge material development has been integrate with existing wafers (either by wafer bonding or direct growth). The different strategies integrating layers Si-based substrates will be reviewed discussed. strain relaxation behavior in high-content SiGe pure shown put serious limitations on possible integration schemes if defects are minimized. A discussion formation SGOI high-temperature oxidation discussed it that residual follows universal trend. This trend allows one design fabricate lattice-engineered heteroepitaxial growth. An analysis thin strained indicates response these crystals also described using simple equilibrium model. Lastly, effective Poisson ratio was measured found vary as function in-plane strain. from near bulk value (0.27) at strain, decrease nearly linearly ∼0.17 4% compressive