Method of producing an interconnect structure for an integrated circuit

摘要: A dual damascene technique that forms a complete via in single step. Specifically, the method deposits first insulator layer (302) upon substrate (300), an etch stop (304) over (302), and second (306) atop (304). mask (308) is then formed by applying photoresist which developed patterned according to locations of dimensions ultimate or vias. Thereafter, may be etched step, for example, using reactive ion etch. The hole (312) through these three layers has diameter via. trench masked into (306). stopped layer. are metallized form interconnect structure. can repeated create multi-level