System for dynamically providing predicted high/slow speed accessing memory to a processing unit based on instructions

摘要: A system (60) for predicting CPU addresses includes a (34) connected by bus (62) to page mode address circuit (64). The (64) is memory arbitration circuits (66) (68). are RAM (42) address, data and control busses (44), (46) (48). (34), the 66 contained in microprocessor integrated (32). 64 examines signals from be supplied at time of SYNC pulse. This operation results examination first byte instruction determine how many following accesses will able carried out high speed mode. If it determined that next access mode, then cycle performed using (42), e.g. access.