Method and system for model-based design and layout of an integrated circuit
作者： Srinivas Doddi , Ya-Chieh Lai , Kuanghao Lay , Weiping Fang , Frank E. Gennari
DOI:
关键词:
摘要: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches allow the directly address effects of manufacturing processes, e.g., identify prevent problems caused by lithography processing. Fast models pattern checking are employed integrate aware processes within EDA such as routers.
lens.org 参考文章(69)
Shin-yi Hsu, System for capturing and using expert's knowledge for image processing ,(2001)
Christophe Pierrat, Chin Aik Le, Process for designing and checking a mask layout ,(1996)
Stephen James Hardy, Kieran Gerard Larkin, Peter Alleine Fletcher, Mark embedding and detection using projective transforms ,(2003)
Shauh-Teh Juang, James Wiley, Jun Ye, Xun Chen, Moshe E. Preil, Method for identifying and using process window signature patterns for lithography process control ,(2006)
Jim Wiley, Ingrid B. Peterson, Mike Von den Hoff, Qualifying patterns, patterning processes, or patterning apparatus in the fabrication of microlithographic patterns ,(2002)
Robert L. Veroff, Christopher M. Lain, Steven T. Eckmann, Gregory H. Chisholm, Reverse engineering of integrated circuits ,(2000)
Moshe E. Preil, Zain K. Saidin, Carl Hess, Yalin Xiong, Lance Glasser, Computer-implemented methods for detecting defects in reticle design data ,(2005)
Moshe E. Preil, Lance Glasser, Gaurav Verma, Methods, systems, and carrier media for evaluating reticle layout data ,(2005)
Youping Zhang, Christophe Pierrat, Facilitating minimum spacing and/or width control during optical proximity correction ,(2001)