Single Poly NVM Devices and Arrays
作者： Richard J. De Souza , Weize Chen , Patrice M. Parris , Xin Lin
DOI:
关键词:
摘要: A single-poly non-volatile memory includes a PMOS select transistor ( 210 ) formed with gate 212 ), and P+ source drain regions 211, 213 in shared n-well region 240 serially connected floating 220 part of p-type layer 222 221, 223 the coupling capacitor 230 over p-well 250 to where first plate second an underlying portion ).
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