Integrated clock differential buffering
作者： Stefan Rusu , Nicholas B. Peterson , Choupin Huang , Vijaya K. Boddu
DOI:
关键词:
摘要: A first phase locked loop (PLL) circuit having a clocking ratio is coupled to receive an input differential clock signal and generates reference signal. second PLL the generate set of output buffers are provide corresponding. The circuits, sets reside within integrated package die at least
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