Numerical comparison of DMOS, VMOS, and UMOS power transistors

作者: A.A. Tamer , K. Rauch , J.L. Moll

DOI: 10.1109/T-ED.1983.21075

关键词:

摘要: Two-dimensional simulation of breakdown voltage and on-resistance DMOS, VMOS, UMOS vertical power devices is performed. The three are evaluated for breakdown-voltage designs 100, 550, 1000 V.

参考文章(2)
J.L. Moll, J.L. Su, A.C.M. Wang, Multiplication in collector junctions of silicon n-p-n and p-n-p transistors IEEE Transactions on Electron Devices. ,vol. 17, pp. 420- 423 ,(1970) , 10.1109/T-ED.1970.16999
R.W. Coen, D.W. Tsang, K.P. Lisiak, A high-performance planar power MOSFET IEEE Transactions on Electron Devices. ,vol. 27, pp. 340- 343 ,(1980) , 10.1109/T-ED.1980.19865