Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion
作者： K. Shenai
DOI: 10.1109/16.52453
关键词:
摘要: The systematic optimization of low-voltage silicon power MOSFET technology is described. It shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from MOSFETs. details discussed include: (1) system impact; (2) unit cell optimization; (3) and process modeling; (4) development; (5) results. optimized include 30-, 50-, 100-V vertical DMOSFETs with optimally scaled gate polysilicon source/drain contacts. Devices the lowest specific on-resistance, input capacitance, improved high-frequency switching have been fabricated excellent wafer yield. This first successful demonstration its impact on high-voltage smart-power technologies. >
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sci-hub.se 参考文章(33)
D.L. Blackburn, Power MOSFET failure revisited PESC '88 Record., 19th Annual IEEE Power Electronics Specialists Conference. ,vol. 2, pp. 681- 688 ,(1988) , 10.1109/PESC.1988.18196
S.C. Sun, J.D. Plummer, Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors IEEE Transactions on Electron Devices. ,vol. 27, pp. 356- 367 ,(1980) , 10.1109/T-ED.1980.19868
T.J. Rodgers, S. Asai, M.D. Pocha, R.W. Dutton, J.D. Meindl, An experimental and theoretical analysis of double-diffused MOS transistors IEEE Journal of Solid-State Circuits. ,vol. 10, pp. 322- 331 ,(1975) , 10.1109/JSSC.1975.1050618
J. F. Burgess, C. A. Neugebauer, G. Flanagan, The Direct Bonding of Metals to Ceramics by the Gas‐Metal Eutectic Method Journal of The Electrochemical Society. ,vol. 122, pp. 688- 690 ,(1975) , 10.1149/1.2134293
K. Shenai, R.S. Scott, B.J. Baliga, Optimum semiconductors for high-power electronics IEEE Transactions on Electron Devices. ,vol. 36, pp. 1811- 1823 ,(1989) , 10.1109/16.34247
V.A.K. Temple, R.P. Love, P.V. Gray, A 600-volt MOSFET designed for low on-resistance IEEE Transactions on Electron Devices. ,vol. 27, pp. 343- 349 ,(1980) , 10.1109/T-ED.1980.19866
V.A.K. Temple, Junction termination extension (JTE), A new technique for increasing avalanche breakdown voltage and controlling surface electric fields in P-N junctions 1977 International Electron Devices Meeting. ,vol. 23, pp. 423- 426 ,(1977) , 10.1109/IEDM.1977.189277
C.P. Ho, J.D. Plummer, S.E. Hansen, R.W. Dutton, VLSI Process modeling—SUPREM III IEEE Transactions on Electron Devices. ,vol. 30, pp. 1438- 1453 ,(1983) , 10.1109/T-ED.1983.21322
P.L. Hower, M.J. Geisler, Comparison of various source-gate geometries for power MOSFET's IEEE Transactions on Electron Devices. ,vol. 28, pp. 1098- 1101 ,(1981) , 10.1109/T-ED.1981.20493
M.S. Adler, V.A.K. Temple, R.C. Rustay, Theoretical basis for field calculations on multi-dimensional reverse biased semiconductor devices Solid-state Electronics. ,vol. 25, pp. 1179- 1186 ,(1982) , 10.1016/0038-1101(82)90077-6