Advanced Analysis of WLCSP Copper Interconnect Reliability under Board Level Drop Test

作者: Tong Yan Tee , Bin Tan Long , Rex Anderson , Shen Ng Hun , Jim Hee Low

DOI: 10.1109/EPTC.2008.4763574

关键词:

摘要: The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and ability to meet miniaturization requirements of portable consumer electronics, such as cell phones. Due differential bending between the silicon die PCB large stiffness difference, board level drop/bend tests are widely accepted methods evaluate damage in parts when a handheld device dropped by consumer. Through an aggressive product development program which includes experiment simulation Amkor has developed next WLCSP (CSPnlTM), exhibits superior reliability subjected drop impact, strong requirement electronics. common industrial qualification criterion withstand at least 40 drops before first failure (FF) under JEDEC test condition 1500 G/0.5 ms. With optimal CSPnl designs, recent results show that typical with size 5.4 mm × minimum failure-free life over 1000 drops. For enhanced design, first-failure 4860 was recorded actual testing. These excellent imply much larger possible future products, opening door wider applications devices, e.g. next-generation electronics greater function integration.

参考文章(17)
Kim Yong Goh, Jing-en Luan, Tong Yan Tee, Drop impact life prediction model for wafer level chip scale packages electronic packaging technology conference. ,vol. 1, pp. 58- 65 ,(2005) , 10.1109/EPTC.2005.1614368
M. Sorricul, Jing-en Luan, Tong Yan Tee, Kim Yong Goh, Hun Shen Ng, X. Baraton, R. Brenner, Drop impact life prediction model for lead-free BGA packages and modules international conference on thermal mechanial and multi physics simulation and experiments in micro electronics and micro systems. pp. 559- 565 ,(2005) , 10.1109/ESIME.2005.1502867
Yi-Shao Lai, Po-Chuan Yang, Chang-Lin Yeh, Effects of different drop test conditions on board-level reliability of chip-scale packages Microelectronics Reliability. ,vol. 48, pp. 274- 281 ,(2008) , 10.1016/J.MICROREL.2007.03.005
Tong Yan Tee, Hun Shen Ng, Chwee Teck Lim, Eric Pek, Zhaowei Zhong, Impact life prediction modeling of TFBGA packages under board level drop test Microelectronics Reliability. ,vol. 44, pp. 1131- 1142 ,(2004) , 10.1016/J.MICROREL.2004.03.005
Tsung-Yueh Tsai, Yi-Shao Lai, Chang-Lin Yeh, Rong-Sheng Chen, Structural design optimization for board-level drop reliability of wafer-level chip-scale packages Microelectronics Reliability. ,vol. 48, pp. 757- 762 ,(2008) , 10.1016/J.MICROREL.2008.01.003
Xuejun Fan, Qiang Han, Reliability challenges and design considerations for Wafer-Level packages international conference on electronic packaging technology. pp. 1- 6 ,(2008) , 10.1109/ICEPT.2008.4607130
Tong Yan Tee, Jing-en Luan, Hun Shen Ng, Development and application of innovational drop impact modeling techniques electronic components and technology conference. pp. 504- 512 ,(2005) , 10.1109/ECTC.2005.1441312
C.T. Lim, C.W. Ang, L.B. Tan, S.K.W. Seah, E.H. Wong, Drop impact survey of portable electronic products electronic components and technology conference. pp. 113- 120 ,(2003) , 10.1109/ECTC.2003.1216265
J.-E. Luan, T.Y. Tee, E. Pek, C.T. Lim, Z. Zhong, J. Zhou, Advanced Numerical and Experimental Techniques for Analysis of Dynamic Responses and Solder Joint Reliability During Drop Impact IEEE Transactions on Components and Packaging Technologies. ,vol. 29, pp. 449- 456 ,(2006) , 10.1109/TCAPT.2006.880455
Tong Yan Tee, Hun Shen Ng, Chwee Teck Lim, E. Pek, Zhaowei Zhong, Board level drop test and simulation of TFBGA packages for telecommunication applications electronic components and technology conference. pp. 121- 129 ,(2003) , 10.1109/ECTC.2003.1216266