Mirror image non-volatile memory cell transistor pairs with single poly layer

摘要: An arrangement of non-volatile memory transistors (11, 13, 15; 21, 23, 25; 31, 33, 35; etc.) constructed in symmetric pairs (14, 30) within the space defined by intersecting word (WL; 22, 24) and bit (BL; 10, 20) lines a array. The have spaced apart sources (32) drains (34) separated channel having floating gate (28; 40, 42) over characteristic electrically erasable programmable read only transistors, except that there is no second poly gate. Only single used as charge storage gate, which placed sufficiently close to source or drain device enable band-to-band tunneling. layer has T-shape, with T-base (42) T-top (40) extending line capacitive relation therewith. program erase combination electrode. A block mode available so can operate flash memory.