Twin eeprom memory transistors with subsurface stepped floating gates
作者： Bohumil Lojek
DOI:
关键词: Electrode 、 Engineering 、 EEPROM 、 Single layer 、 Memory array 、 Electrical engineering 、 Transistor 、 Bit line 、 Electric field
摘要: A memory array (10) with cells (13) arranged in rows and columns each cell having twin EEPROMs (15, 115) featuring subsurface stepped (53, 54) floating gates for electric field concentration. The employ only a single layer of poly, one portion being gate (82, 84) EEPROM another word lines (WL1, WL2). share common electrode (92) by diffused control (62, 64) bit line (BL1). are symmetric across the electrode.
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