Mirror image memory cell transistor pairs featuring poly floating spacers

摘要: By arranging floating spacer (27, 29) and gate (17, 19) non-volatile memory transistors in symmetric (31) pairs, increased chip density may be attained. For each pair of such transistors, the gates are laterally aligned with spacers appearing on outward edges gate. At inward edges, two share a common drain electrode (25). The independent other except for shared electrode. Tunnel oxide (30) separates from gate, but both maintained at potential, thereby providing dual paths charge exiting tunnel oxide, as charged is propelled by programming voltage. pairs can columns (e.g., Fig. 18) direction orthogonal to forming array.