Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
作者： Shen-Yang Lee , Han-Wei Chen , Chiuan-Huei Shen , Po-Yi Kuo , Chun-Chih Chung
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摘要: For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of $5.3\times9$ nm2 and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit remarkable Ion–Ioff ratio more than 108. We demonstrated channels, double layers, GAA NC-FET threshold voltage ( ${V}_{\textit {TH}}$ ) 0.61 V, superior subthreshold behavior average minimum sub- slope 43.85 26.84 mV/dec, respectively. An additional ZrO2 seed layer was inserted under Hf $_{{1-}{x}}$ ZrxO2 to improve ferroelectric crystallinity. Thus, conventional crystallization annealing step can be omitted due presence orthorhombic phase ${o}$ -phase) before further post-metal (PMA).
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