Stabilization of SiO 2 passivation layers with P 2 O 5

摘要: Measurements are reported on the stability of planar, npn silicon transistors with and without a phosphosilicate glass layer over SiO2 passivation layer. The forms during emitter diffusion from P2O5 source, data show that, to insure stability, it must not be removed in subsequent processing steps. units tested were conventional geometry except for gate electrode base region, which provided additional information surface conditionT. he subjected temperatures 150° 200°C either gate-bias or junction reverse-bias. Production transistors, gates, had failed life test shown have no because been by excessive etching fabrication. Additional evidence stabilization has obtained using metal-oxide-silicon capacitors treatment Both dc conduction through insulator capacitance-voltage characteristic measured. These experiments suggest that transistor degradation unstabilized is caused an accumulation positive space-charge silicon-dioxide. This charge accumulates when electric field (directed toward silicon) applied at range 150°C.