Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices
作者： Alastair M. Smith , George A. Constantinides , Peter Y. K. Cheung
DOI: 10.1109/TVLSI.2008.2000259
关键词:
摘要: This paper is concerned with the application of formal optimization methods to design mixed-granularity field-programmable gate arrays (FPGAs). In particular, we investigate appropriate mix and floorplan heterogeneous elements: multipliers, RAMs, lookup table (LUT)-based logic, in order maximize performance a set digital signal processing (DSP) benchmark applications, given fixed silicon budget. A mathematical programming framework introduced, along heuristics, capable providing upper-bounds on achievable reconfigurable-to-fixed-logic ratio. Moreover, use linear-programming bounding procedures from operations research community provide lower-bounds same quantity. Our results provide, for first time, quantifications optimal performance/area-enhancing capability multipliers RAM blocks within system context. The approach detailed provides mechanism explore future technology nodes.
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