Slack redistribution for graceful degradation under voltage overscaling

摘要: Modern digital IC designs have a critical operating point, or “wall of slack”, that limits voltage scaling. Even with an error-tolerance mechanism, scaling below - so-called overscaling results in more timing errors than can be effectively detected corrected. This the effectiveness trading off system reliability and power. We propose design-level approach to (power) in, e.g., microprocessor designs. increase range values at which (timing) error rate is acceptable; we achieve this through techniques for power-aware slack redistribution shift frequently-exercised, near-critical paths power- area-efficient manner. The resulting heuristically minimize maximum allowable encountered, thus minimizing power consumption prescribed allowing design fail gracefully. Compared baseline designs, 32.8% average 12.5% reduction 2%. area overhead our techniques, as evaluated physical implementation (synthesis, placement routing), no 2.7%.