EVAL: Utilizing processors with variation-induced timing errors

摘要: Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, prevent any resulting timing errors, we design processors for worst-case parameter values, may lose substantial performance. An alternate approach explored this paper is closer nominal and provide some transistor budget tolerate unavoidable variation-induced errors. To assess approach, first presents novel framework that shows how microarchitecture techniques can trade off errors power processor frequency. Then, the introduces an effective technique maximize performance minimize presence namely High-Dimensional dynamic adaptation. For efficiency, implemented using machine-learning algorithm. The results show our best configuration increases frequency by 56% on average, allowing cycle 21% faster without variation. Processor 40% 14% higher - at only 10.6% area cost.