Method and system for selectively disabling simulation model instrumentation
作者： Wolfgang Roesner , John Fowler Bargh , Bryan Ronald Hunt , Derek Edward Williams
DOI:
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摘要: A method and system are disclosed that utilize the expressiveness of hardware description languages for selectively disabling instrumentation during simulation a digital circuit design. According to present invention, an entity, described utilizing language include output signal indicate occurrence event simulation, is implemented into model Next, associated with unique storage element. Finally, disable mechanism uniquely said provided, such may be masked by element testing
google.co.in 参考文章(8)
Lee D. Whetsel, Event qualified testing protocols for integrated circuits ,(1991)
Michael John Zroka, Ronald Joseph Sullivan, Behavioral language models for testing and verification of digital electronic circuits ,(1996)
Richard Raimi, Carl Pixley, Measurement of digital circuit simulation test coverage utilizing BDDs and state bins ,(1995)
Stephen P. Sample, Distributed logic analyzer for use in a hardware logic emulation system ,(1998)
L. Whetsel, Event qualification: a gateway to at-speed system testing Proceedings. International Test Conference 1990. pp. 135- 141 ,(1990) , 10.1109/TEST.1990.114011
Mikhail Bershtevn, Stephen P. Sample, Method and apparatus for design verification using emulation and simulation ,(1997)
L. Whetsel, At-speed board test simplified via embeddable data trace/compaction IC autotestcon. pp. 307- 315 ,(1991) , 10.1109/AUTEST.1991.197567