Bit line switch array for electronic computer memory

摘要: A cache memory having rows of cells, each row at least first and second blocks cells. Each cell stores a data signal, has one word line input, bit input/output. connects the inputs first, second, third, fourth cells in memory. The third are contained block, while block. First sense amplifiers or write drivers provided for reading from writing to switches control connect inputs/outputs respectively, amplifier/write driver. Third switchably capable being independently actuated. Selection means, such as an address decoder, actuate either only block amplifiers, both amplifiers.