Method of fabricating chip scale package
作者： In-ho Hyun , Ju-seok Maeng
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摘要: A chip scale package (CSP) fabricating method is provided. In this method, CSP chips are fabricated on a wafer and subjected to an electric die sorting (EDS) process. Then, determined be non-defective through the FDS process packaged into strip. strip final test. test singulated individual CSPs. Following this, CSPs surface-mounted module board. Substantially all of board subsequently burn-in tested. As result, productivity improved, manufacturing costs reduced.
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