Versatile bus interface macro for dynamically reconfigurable designs

作者: Jeffrey M. Mason , W. Story Leavesley

DOI:

关键词: Control reconfigurationMultiplier (economics)Logic blockEmbedded systemMacroComputer scienceBlock ramBus interface

摘要: Method and apparatus for module design in a PLD is described. In one example, includes reconfigurable module, static at least logic interface macro. The signal configured active partial reconfiguration. interface. Each macro first pins coupled to the of second module. are disposed an implementation area embodiment, each slice configurable block (CLB). some embodiments, implemented using another type block, such as RAM and/or multiplier block.