Structure and method to improve threshold voltage of mosfets including a high k dielectric
作者： Edward P. Maciejewski , Effendi Leobandung , Sunfei Fang , Brian J. Greene , Yanfeng Wang
DOI:
关键词: Semiconductor 、 Conformal map 、 Optoelectronics 、 Threshold voltage 、 Silicon oxide 、 Gate oxide 、 Dielectric 、 Materials science 、 Gate dielectric 、 Thin layer
摘要: A method of forming threshold voltage controlled semiconductor structures is provided in which a conformal nitride-containing liner formed on at least exposed sidewalls patterned gate dielectric material having constant greater than silicon oxide. The thin layer that using low temperature (less 500° C.) nitridation process.
lens.org 参考文章(18)
Shinpei Iijima, Masayoshi Saito, Kanta Saino, Eiji Kitamura, Yoshiki Kato, Kiyonori Oyu, Satoru Yamada, Semiconductor device having gate electrode of polymetal gate structure processed by side nitriding in anmonia atmosphere ,(2004)
Luigi Colombo, Encapsulated MOS transistor gate structures and methods for making the same ,(2004)
Chuan-Li Chang, Di-Son Kuo, Chang Song Lin, Ming-Chou Ho, Hsin-Ming Chen, Wen-Ting Chu, Modified nitride spacer for solving charge retention issue in floating gate memory cell ,(2000)
Dureseti Chidambarrao, Omer H. Dokumaci, Embedded stressed nitride liners for CMOS performance improvement ,(2004)
Nestor A Bojarczuk, Eduard A Cartier, Paul C Jamison, Vamsi K Paruchuri, Vijay Narayanan, Supratik Guha, Martin M Frank, Cyril Cabral, Rajarao Jammy, Evgeni P Gousev, Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide ,(2005)
James J. Quinlivan, James S. Nakos, Jay S. Burnham, John J. Ellis-Monaghan, Selective nitridation of gate oxides ,(2006)
Chia-Lin Chen, Mo-Chiun Yu, Chien-Hao Chen, Method of generating multiple oxides by plasma nitridation on oxide ,(2004)
Nestor A. Bojarczuk, Eduard A. Cartier, Vamsi K. Paruchuri, Vijay Narayanan, Supratik Guha, Martin M. Frank, Cyril Cabral, Matthew W. Copel, Rajarao Jammy, Evgeni P. Gousev, SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH-k DIELECTRICS ,(2004)
Katy Schabernack, Fabian Koehler, Falk Graetsch, Method for encapsulating a high-K gate stack by forming a liner at two different process temperatures ,(2009)
Eduard A. Cartier, Vamsi K. Paruchuri, Bruce B. Doris, Vijay Narayanan, Keith Kwong Hon Wong, Matthew W. Copel, Rajarao Jammy, Young-Hee Kim, Barry P. Linder, Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled cmos devices ,(2006)