Packing density for flash memories

摘要: Improved packing density as well improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation covered with a thin nitride layer. The confinement of the planarization, preferably self-limiting chemical/mechanical polishing process, to surface layer covering structures. Gate oxide control electrode connections can then be formed on substantially planar without compromising quality or breakdown voltage device must withstand for programming. Since severe topology avoided over which these are formed, formation low resistance connections, possibly including metal possible allow scaling transistors cells scaled sizes not previously possible.