Logic transistor and non-volatile memory cell integration
作者： Mark D. Hall , Mehul D. Shroff
DOI:
关键词: Masking (art) 、 Layer (electronics) 、 Transistor 、 Non-volatile memory 、 Optoelectronics 、 Barrier layer 、 Gate oxide 、 Materials science 、 Electrical conductor 、 Electronic engineering 、 Logic gate
摘要: A first conductive layer and an underlying charge storage are patterned to form a control gate in NVM region. dielectric barrier formed over the gate. sacrificial is planarized. masking region which defines select location laterally adjacent second logic location. Exposed portions of removed such that portion remains at planarized expose portion. The result opening exposes layer.
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