Interconnect structure and method
作者： Chen Chien-Han , Ho Chun-Te , Chiu Chien-Chih , Liang Ming-Chung
DOI:
关键词: Dielectric 、 Etching (microfabrication) 、 Diffusion barrier 、 Line (electrical engineering) 、 Substrate (electronics) 、 Layer (electronics) 、 Optoelectronics 、 Electrical conductor 、 Trench 、 Materials science
摘要: An embodiment includes a method. The method includes: forming first conductive line over substrate; depositing dielectric layer the line; second layer, including different material than layer; patterning via opening in and where is patterned using etching process parameters, parameters; trench diffusion barrier bottom along sidewalls of opening, opening; filling with material.
lens.org 参考文章(21)
Chai Der Yen, Fu-Cheng Chang, Hung-Che Liao, Cheng-Pang Yeh, Hung-Yu Chiu, Dual damascene process and apparatus ,(2012)
Se-Woong Park, Kil-Ho Lee, Ki-Joon Kim, Semiconductor Structures and Methods of Manufacturing the Same ,(2013)
Masaya Kawano, Yoshiaki Yamamoto, Takamasa Ito, Semiconductor device with interconnection structure for reducing stress migration ,(2007)
Ting Cheong Ang, Victor Seng Keong Lim, Young-Way Teh, Novel copper metal structure for the reduction of intra-metal capacitance ,(2001)
Chih-I Wu, Jihperng Leu, Hyun-Mog Park, Method of making a semiconductor device by forming a masking layer with a tapered etch profile ,(2002)
Chewn-Pu Jou, Tse-Hua Lu, Low Cost Metal-Insulator-Metal Capacitors ,(2010)
Cheng-Lin Huang, Shau-Lin Shue, Ching-Hua Hsieh, Via structure with improved reliability ,(2005)
Atsunobu Isobayashi, Yoshihiro Uozumi, Restoration method using metal for better cd controllability and cu filing ,(2009)
Sven Mueller, Volker Jaschke, Tino Hertzsch, Kai Frohberg, Reduce critical dimensions of vias and contacts through the device level of semiconductor devices ,(2008)