CMOS reference voltage generation
作者： Eugene R. Bukowski , Charles R. Hoffman
DOI:
关键词:
摘要: A process insensitive reference voltage generator includes a first and second identical FET devices coupled in parallel configuration with biasing network, of devices, interconnecting the substrate terminal device to node formed between positive supply ground potential. The control is connected whose potential different from that node. source terminal. terminals both are respective input an operational amplifier output said device.
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