Fast single-photon imager acquires 1024 pixels at 100 kframe/s

摘要: We present the design and we discuss in depth operating conditions of a two-dimensional (2-D) imaging array of single-photon detectors that provides total 1024 pixels, laid out 32 rows by columns array, integrated within a monolithic silicon chip with dimensions 3.5 mm x mm. employed standard high-voltage 0.35μm CMOS fabrication technology, no need any custom processing. Each pixel consists one Single-Photon Avalanche Diode (SPAD) compact front-end analog electronics followed by digital processing circuitry. The in-pixel senses ignition avalanche, quenches the detector, pulse restores detector for detecting subsequent photon. circuitry counts events (both photon unwelcome "noise" ignition) user-selectable integration time-slots stores count into an memory cell, which is read-out 10 ns/pixel. Such two-levels pipeline architecture allows to acquire actual frame while contemporary reading previous one, thus achieving very high free-running rate, negligible inter-frame dead-time. Each therefore completely independent photon-counter. measured Photo Detection Efficiency (PDE) tops 43% at 5V excess-bias, Dark-Counting Rate (DCR) below 4kcps (counts per second) room temperature. maximum frame-rate depends on system clock; convenient 100MHz clock achieved speed 100 kframe/s from all pixels.