Vertical architecture for enhancement mode power transistors based on GaN nanowires

摘要: The demonstration of vertical GaN wrap-around gated field-effect transistors using nanowires is reported. with smooth a-plane sidewalls have hexagonal geometry made by top-down etching. A 7-nanowire transistor exhibits enhancement mode operation threshold voltage 1.2 V, on/off current ratio as high 108, and subthreshold slope small 68 mV/dec. Although there space charge limited behavior at source-drain voltages (Vds), the drain (Id) transconductance (gm) reach up to 314 mA/mm 125 mS/mm, respectively, when normalized nanowire circumference. measured breakdown around 140 V. This approach provides a way next-generation GaN-based power devices.