作者: Sheng Hsiung Chen , Ming-Hsing Tsai
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摘要: A novel and improved method of fabricating an integrated circuit, in which special copper films are formed by a combination physical vapor deposition (PVD), chemical mechanical polish (CMP) electrochemical (ECD) techniques. The methods the present invention make efficient use several process steps resulting less processing time, lower costs higher device reliability. By these techniques, high aspect ratio trenches can be filled with without problem dishing. special, selective metal is utilized taking place only on seed layer trench. This auto-plating or “plate-up” occurs trench provides good sealing around perimeter fine coverage for subsequent robust interconnects. plating film that easily removed tends to more uniform free usual defects associated CMP films.