NAND flash depletion cell structure

摘要: NAND architecture Flash memory strings, arrays, and devices are described that utilize depletion mode floating gate cells. Depletion cells allow for increased cell current through lower channel r dS resistance decreased “narrow width” effect, allowing scaling of strings. In addition, the required voltages reading programming operations reduced, use more efficient, voltage charge pumps a reduction circuit element feature sizes layouts. Cell inhibit unselected is also increased, reducing likelihood disturb in array. Operation speed improved by increasing read selected string ability to overcome RC time constants lines capacitances lowered swings supplies.