Segmented non-volatile memory array with multiple sources with improved word line control circuitry

摘要: A flash memory array arrangement having a plurality of erase blocks which can be separately erased, preferably using negative gate techniques. The cells are arranged in each block to form an cell rows and columns, with the sources connected common source line so as permit separate erasure. Cells located row have their control gates word one columns drains bit line. Word circuitry functions state lines read, program operations. Separate transistors for purpose connecting erased voltage. associated other than being cause that erasure will not occur those deselected blocks.