Bit and block erasing of an electrically erasable and programmable read-only memory array
作者： Sung-Wei Lin , Manzur Gill , David Mcelroy , Iano D'arrigo
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摘要: A method for either block- or bit-erasing is described an array of EEPROM cells, each having transistor channel regions with subchannels thereof respectively controlled by a floating gate conductor and control gate. Erasing occurs through Fowler-Nordheim tunnel window (34) between source bit line (24) (42) selected cell. For one more first second erasing voltages are such that the positive than word (48) voltage sufficient to cause excess electrons on be drawn region (24). The nonselected lines have nonerasing impressed thereon sufficiently close no erase disturb will occur in cells.
lens.org 参考文章(10)
Fritz G. Adam, Integrated DDC memory with bitwise erase ,(1977)
John Flackett Dickson, Raymond Edward Oakley, Content addressable memories ,(1975)
Andrew C. Tickle, Electrically erasable programmable read-only memory ,(1981)
Ting-Wah Wong, Gheorghe Samachisa, Chien-Sheng Su, George Smarandoiu, Block electrically erasable eeprom ,(1987)
Kamesawara K. Rao, EEPROM utilizing single transistor per cell capable of both byte erase and flash erase ,(1988)
Eliyahou Harari, Electrically erasable non-volatile semiconductor memory ,(1977)
Norman E. Moyer, Electrically erasable programmable read only memory cell having a single transistor ,(1982)
Lawrence S. Wall, Electrically alterable floating gate semiconductor memory device ,(1976)
Erwin Jacobs, Memory cell having a double gate field effect transistor and a method for its operation ,(1982)
David D. Wilmoth, James L. Paterson, Bert R. Riemenschneider, Erasable programmable memory including buried diffusion source/drain lines and erase lines ,(1987)